Speed Efficient Vlsi Design of Lifting Based 2d Dwt Architecture Using Vedic Mathematics

This paper presents VLSI architecture for lifting based 2D DWT architecture with reduced delay. The proposed structure offers high speed and high area efficiency. Fast computation is achieved by replacing conventional multiplier units of DWT architecture with Vedic multiplier. Three sutras of Vedic multiplication are employed to reduce logic shifting operations of multiplier units and so high speed is made possible. The computation techniques of three DWT structures have been compared to prove high performance of proposed 2D DWT architecture. The proposed 2D DWT architecture is modelled and implemented using XILINX ISE 9.1.